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Using ModelSim with Quartus II Block Design FilesA Block Design File to VHDL File Converter and ModelSim StarterJesse op den BrouwThe Hague University Of Applied [email protected] 20, 2018

AbstractStudents at The Hague University Of Applied Sciences get their first glimpse at Digital Designeducation using only schematic entry using the Quartus II software environment. Schematicentry is done using a full screen WYSIWYG editor and generates Block Design Files (BDFfiles). This is a proprietary file type and is not supported outside the Quartus II environment.Simulation is at this stage unknown to them. We try to hide as much as possible as notto distract their attention from the design process.ModelSim is a full fledged VHDL and Verilog simulator and widely spread amongst digitalsystem designers, but is unable to compile and simulate Quartus’ BDF files.Quartus provides an option to convert BDF files to VHDL files. Converting BDF files toVHDL files is a tedious and error prone operation and has to be done every time the designis updated.This document describes a set of files as part of a design flow that deals with all of theproblems mentioned above. The scripts run both on Windows and Linux operating systems.Both the Subscription Edition and the Web Edition are supported.

CONCEPTContents1 Introduction32 A Typical Quartus Project Setup43 The Script’s Environment54 Quick overview of the script65 The Script’s Internal Working76 Setting up a ModelSim command file147 Installation and use of the script in a design flow148 Things to Remember169 Known Issues16A The Complete Tcl Script17B The Design Flow File23C An Example of a Install Script on Windows24D Changelog & To Do26Using ModelSim with Quartus II Block Design Files1

CONCEPTListings12345678910111213141516Set ModelSim Path . . . . . . . . . . . . . . . . . . . . . . . . .Print a nice banner . . . . . . . . . . . . . . . . . . . . . . . . .Check for open project . . . . . . . . . . . . . . . . . . . . . . .Determine the install path of the ModelSim executable . . . . .Set the project directory . . . . . . . . . . . . . . . . . . . . . .Check the database . . . . . . . . . . . . . . . . . . . . . . . . .Find the file containing top level entity . . . . . . . . . . . . . .Create a list of all BDF files in the project directory . . . . . . .Create VHDL files . . . . . . . . . . . . . . . . . . . . . . . . . .Remove all VHDL files for which a BDF file exists but not in theronment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Check the top level and start ModelSim. . . . . . . . . . . . . .Including all VHDL Files in a Modelsim Command File. . . . . .The Design Flow File . . . . . . . . . . . . . . . . . . . . . . . .The Complete Script. . . . . . . . . . . . . . . . . . . . . . . . .The Design Flow File . . . . . . . . . . . . . . . . . . . . . . . .An Example of a Install Script on Windows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .project envi. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .777799101011.4561512131415172324List of Figures1234Converting a Block Design File to an HDL File. . .An example of a completed design flow. . . . . .An example output of the script. . . . . . . . . . .The BDF Conversion And Simulation Design Flow.Using ModelSim with Quartus II Block Design Files.2

CONCEPT1IntroductionStudents of the faculty of Electrical Engineering at the The Hague University of AppliedSciences1 [1] get acquainted with digital design in the first year of their study. The learningline consists of three courses.In the first course they learn the basics of digital design like number systems, booleanalgebra, logic gates, K-maps and some elementary knowledge of latches and flip-flops. Atthis stage, they do not use VHDL or any other HDL, and they do not know anything aboutsimulation.For practical work, the students use the Quartus II design software from Altera. Ashardware platform, they use the DE0 Digital Systems Board supplied by Terasic [2]. Itconsists of a Cyclone III FPGA with about 15,000 cells, LEDs, switches, push buttons andseven segment displays.All the practical work in the first course is done using schematic entry and using logicgates to complete the assignments. They do use hierarchies. The students use simulation butonly to verify if their solution is correct; all the simulation scripts and testbenches have beenprepared by faculty staff.Schematic designs are saved in so-called Block Design Files. Block Design Files are proprietary files to Quartus. These files, recognizable by the extension .bdf, can be synthesizedusing the Quartus software.Simulation is done with Modelsim. ModelSim is a well known and widespread VHDLand Verilog simulator, but is unable to compile and simulate BDF files.Fortunately, Quartus has an option to convert BDF files to VHDL or Verilog files. This canbe done by opening the appropriate BDF file and using the Create HDL File option. You cansee a screenshot in Figure 1.Of course, this has to be done for every file in the project and every time the files havechanged. This is not only dull, but also error prone. You can easily forget to convert achanged file, render the design useless.This document describes a set of files that deals with all of the problems mentionedabove. There are two files: a script that handles the conversion of Block Design Files toVHDL files and starts ModelSim automatically, and a file that will set up the script as part ofa so-called design flow. The files run both on Windows and Linux operating systems. Boththe Subscription Edition and the Web Edition are supported.This document consists of eight sections. Section 2 describes more about how a typicalproject is set up. Section 3 describes the environment the script runs in. Section 4 containsa first description on what the scripts actually does. Section 5 gives an in-depth explanationof the script’s internal working. Section 6 gives some hints on how to set up a genericModelSim command file. Section 7 describes the installation of the script and the designflow file. Section 8 gives some notes on things to avoid when creating schematics. At last,Section 9 deals about some known issues.The intended audience are designers who make use of Block Design Files and want touse ModelSim as their favorite simulator, and faculty staff who want their students to useschematic entry of digital systems (and of course use ModelSim for simulation).Please note that the script hasn’t been tested with Mega Functions or MaxII functions,only with primitive functions such as AND, OR, and NOT.There is a similar script for converting BDF files to Verilog files by Chris Zeh. See [3].1In Dutch: De Haagse HogeschoolUsing ModelSim with Quartus II Block Design Files3

CONCEPTFigure 1: Converting a Block Design File to an HDL File.2A Typical Quartus Project SetupBefore we tell more about the internals of the script it’s best to give an overview of a typicalQuartus project suited for this setup.For the script to work, there are two true obligations: the name of the ModelSim command file must consist of the prefix tb followed by the name of the top level design entity(which is not the design entity name of the testbench) and the extension .do, and the nameof the top level design entity must be the same as the first part of the design filename. Thereare really no other obligations (even the top level filename can differ from the top levelentity name, but it is included to force students to use some sensible filenames). Note thatfor BDF files, the name of the design entity is always the same as first part of the filename.Also note that this is not always true for HDL files. So if there’s a top level design entitywith the name full adder, the corresponding filename must be full adder.bdf (orfull adder.vhd as an example). It’s good practice though to keep the filename of thetestbench as close as possible to the design entity filename, so the name of the corresponding testbench filename should the same as the top level entity name with the prefix tb andthe extension .vhd. The typical project has the following files:full adder.bdf - the Block Design File with the top level design entitytb full adder.vhd - the testbench filetb full adder.do - the ModelSim command fileIt’s possible to use hierarchies, consisting of multiple BDF files. The script is able to processall BDF files in the current project. It’s also possible to incorporate more that one ModelSimUsing ModelSim with Quartus II Block Design Files4

CONCEPTcommand file to simulate multiple (sub) designs. The only thing you have to do is to changethe top level design entity name in the Quartus environment (and run Analysis and Synthesis,see Section 9).The project may contain other file types such as VHDL and Verilog files. The script willnot touch these files as long as they are not generated from BDF files.Only BDF files visible in the project environment (the files you see in the Files tab of theProject Navigator in the Quartus IDE) are processed, all other BDF files are not processed.Rationale for this is that you probably created the BDF file in the course of the project andforgot to delete the file when is wasn’t needed anymore. Note however that all VHDL filesassociated with such BDF files are removed. This way, ModelSim will not compile them whenusing the code in Listing 12 in Section 6 (and it seems odd to have those VHDL files lingeron).It is possible to use a VHDL or Verilog file as the top level design entity. When instantiating designs from BDF files, you can just use the design entity names. Note that in thecorresponding VHDL files, the architecture name is always bdf type.3The Script’s EnvironmentThe script has to be installed as part of a so-called design flow. A design flow is a list of tasksthat have to be done in order to fulfil the design’s needs. Mostly, you have to synthesize thedesign, run the timing analyser and create a programming file for the device. Figure 2 givesan example of a completed flow.Figure 2: An example of a completed design flow.The script is written in Tcl (”tickle”). Tcl is a scripting language, a language designedfor automating tasks which could be done by hand by an human operator. The languageprovides a full set of flow control statements, functions and a lot of routines (in Tcl they allare called commands). For a introductory course on Tcl, see [4] and [5].The Quartus environment heavily uses Tcl for scripting purposes and provides a set ofpackages. The packages provide an interface to Quartus’ internal information. The scriptmakes use of the ::quartus::project Tcl package. More information can be foundin [6]. Examples are: finding the top level design name, the project directory. For anextensive overview and examples, see [7] and [8].The script makes use of the quartus map command. This command is able to do alot of things for you: create the design database, convert files, analysis and synthesis. SeeQuartus AN309citation needed .When the script runs, it prints information in the System tab of the Message window.This is done by the post message command, optionally followed by a message type. Anexample of some output can be seen in Figure 3.Using ModelSim with Quartus II Block Design Files5

CONCEPTNote there’s no way to pass arguments to the script, so you can’t pass the name of theModelSim command file. That’s why the script always presumes a filename as described inSection 2.Figure 3: An example output of the script.4Quick overview of the scriptThis script does a number of things, but mainly it converts all BDF files in the current projectenvironment into VHDL files and starts ModelSim with an associated command file. Ofcourse there are a lot of build-in checks to determine if conversion and simulation is at allpossible. A list of stages is given below:1. Checks if the project is open.2. Finds ModelSim execution path if none is provided. Linux and Windows supported.3. Creates a project database if none is found.4. Finds the top level entity name, checks if the top level entity name has an associatedfile, complains if none is found.5. Loops through all BDF files found in the project environment and creates associatedVHDL files if needed.6. Removes all VHDL files from associated BDF files in the project directory but not in theproject environment, but not VHDL files that do NOT have a associated BDF file27. Finds top level filename and creates DO filename.8. Starts ModelSim with DO filename.2You probably have to read this sentence twice. See Section 5 for details.Using ModelSim with Quartus II Block Design Files6

CONCEPT5The Script’s Internal WorkingFor the impatients: a complete printout of the script can be found in Appendix A.The script starts with a lot of comment explaining the working of the script in shorthand.The script is unable to handle arguments due to the fact that it is called as part of a flow bythe Quartus GUI. There is only one user option available as you can see in Listing 1. If youdon’t want the script to find the ModelSim install path, please fill in the user option.123# User input: set to the modelsim path. Keep empty for autodetect.#set modelsim exec path "/opt/altera/12.1sp1/modelsim ase/linuxaloem/vsim"set modelsim exec path ""Listing 1: Set ModelSim PathJust as any script, it first prints a pretty banner. Currently, we have version 1.3 available.See Listing 2.1234# Print a nice bannerpost message -type info t message -type info "BDF to VHDL converter & ModelSim Starter v1.3"post message -type info ting 2: Print a nice bannerIn the first stage, the script checks if there is there is an opened p