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Quartus II TutorialSeptember 10, 2014Quartus II Version 14.0This tutorial will walk you through the process of developing circuit designs within Quartus II,simulating with Modelsim, and downloading designs to the DE-1 SoC board.Note that the steps we show you here will be used throughout the class – take notes, andrefer back to the appropriate sections when you are working on future labs.1. Installing Quartus II SoftwareMost of the designs in this class will be done through the Altera Quartus II software. This ispreloaded on machines in the EE department, and you are free to do all the work on thesePCs. However, if you have a PC of your own that you would like to use, you can install thesoftware there as well.If you do not want to set up Quartus on your own machine, skip to the next section.To install the software on your own PC, grab the Quartus 14.0 software from the EE271website. You’ll need both the Quartus software tarfile, and the CycloneV qdz file. Save theseboth to the same directory.Extract the “tar” file (I use 7zip, but other tools are out there), and then run the setup.bat file.Make sure you select the “ModelSim-Altera Starter Edition” when running setup.bat. Installthe optional components as well.Run Quartus II. If it asks about installing devices, say yes (if it doesn’t ask, then likely the filesfor the Altera devices were already installed). The directory with the Quartus II device files isthe directory you downloaded the individual file into previously. You want to install theCyclone V files.2. Getting Started in Quartus IIIn this class we will do multiple labs using the Quartus II software. As part of this, we willcreate multiple files for your designs, for testing your designs, and for downloading yourdesign to the DE-1 SoC board. To keep things sane, you should create an overall classdirectory, and then a subdirectory under that when you start each lab. So, you might havean “ee271labs” directory, and create a “lab1” subdirectory for lab #1. Do not reuse the samedirectory for different labs, since you’ll want to refer back to a working design when youdevelop each new lab. However, when you start each lab after #1, copy the previousdirectory over as the new directory so that you can reuse many of the files and the setup youdid in previous labs.

If you are using the lab machines, put your work onto your U: drive (shared across allmachines). If you are using your own machine, you can store the files where-ever you’llremember them.Get the lab #1 files from the class website, and put them into the subdirectory you justcreated (note: you need to copy them to the new directory – if you leave them in the ZIP fileyou downloaded from the website you’ll have problems). These files will help you get startedquickly with Quartus.3. Creating Verilog Files in QuartusIn the previous steps we created a directory, and moved in files to set up a Quartus project,which told the tool about the DE1 SoC board we are using. We now need to add some actualcircuitry to the project. We will create a simple design of a 2:1 Mux – this is a device with twodata inputs i0 and i1, and a select input sel. When sel 0 the output is equal to the i0 input,while when sel 1 the output is equal to the i1 input.Start Quartus II by double-clicking on the DE1 SoC.qpf file, which is the main Quartus file forthis project. Your PC may hide the file extension, so if you just see “DE1 SoC”, point to it andmake sure the pop-up information text says “QPF File”.We now need to create a SystemVerilog file (System Verilog is “modern” Verilog, with a lotof nice features over previous basic Verilogs. We will use System Verilog exclusively in thisclass). Go to File New (or just hit control-N), select “SystemVerilog HDL File”, and hit “OK”.You will do this whenever you want to create a new Verilog file.The new file is opened up for you in Quartus’s text editor in the middle of the tool. Note thatthe file doesn’t have a specific name yet –fix that by hitting “File Save As”. Then give it thename “mux2 1.sv” and save the file. Note that in Verilog the filename MUST be the same asthe module you are designing, and in this case we are designing a module called “mux2 1”.

You should notice that the title bar for the editor pane has now changed to “mux2 1.sv”. Wenow need to put in the circuitry that we are developing. You can type in the following (or justcut-n-paste it in) to the mux2 1.sv window.module mux2 1(out, i0, i1, sel);output out;input i0, i1, sel;assign out (i1 & sel) (i0 & sel);endmodulemodule mux2 1 testbench();reg i0, i1, sel;wire out;mux2 1 dut (.out, .i0, .i1, .sel);initial beginsel 0; i0 0;sel 0; i0 0;sel 0; i0 1;sel 0; i0 1;sel 1; i0 0;sel 1; i0 0;sel 1; i0 1;sel 1; i0 1;endendmodulei1 0;i1 1;i1 0;i1 1;i1 0;i1 1;i1 0;i1 1;#10;#10;#10;#10;#10;#10;#10;#10;This creates the module we are developing (“mux2 1”), as well as a tester module(“mux2 1 testbench”) that will help us check whether the design is correct.

4. Synthesizing a designNow that we have the design created in Quartus, we need to check that it is valid Verilog.First, we need to inform Quartus that the mux2 1 file is the “top-level” of the design – as wego through the class we will create designs with many different modules all talking to oneanother, and Quartus needs to know which of the files holds the top-level, complete design.Since we have a 1-file circuit this is pretty easy. In the upper-left side of Quartus is the“Project Navigator”. Make sure the “Files” tab at the bottom of the Project Navigator isselected, and right-click on the file “mux2 1.sv”. Select “Set as Top-Level Entity”.You can now have Quartus check whether the design is at least syntactically correct (i.e. youdidn’t make any spelling mistakes or the like). Look at the top toolbar for the blue checkmarkwith the purple triangle and the tiny gate symbol. Press that button, which will startQuartus’s Analysis and Synthesis steps.The tool should run for a little while, and then tell you in the message window (near thebottom of Quartus) that “Analysis & Synthesis was successful”. If it does not, then check yourdesign and any error messages found in the message window – you can usually double-click

on the error message and it will take you to exactly where Quartus thinks the error is. Correctthe problems, and re-run Analysis & Synthesis.Once Quartus declares success, we know that the file is correct Verilog. However, we don’tknow whether the design is a proper implementation of the desired functionality. For that,we will simulate the design, which uses the ModelSim simulator to show the actual behaviorof our design.5. Simulating a designIn addition to Quartus II, we will be using the ModelSim software, which can simulate Verilogdesigns for you. To help make using the tool easier, we provide three files on the website tohelp:Launch ModelSim.bat: A file to start ModelSim with the correct working directory.runlab.do: A command file for ModelSim that will compile your design, set up thewindows for the design, and start simulation.mux2 1 wave.do: A default file that sets up the simulation window properly.You already added these files into the lab1 directory in a previous step.To start ModelSim, double-click the “Launch ModelSim.bat” file. This should show the blue“ModelSim” title screen and start ModelSim. If you instead saw a black window flash by andnothing happened, then your ModelSim is installed at a non-standard location; edit the“Launch ModelSim.bat” file by right-clicking the file, and put in the correct path to theModelsim.exe executable, save the file, and retry starting ModelSim.Once ModelSim is started, we can now simulate our circuit. At the bottom of the window isthe “Transcript” pane. We can issue commands here, and see ModelSim’s responses. Formux2 1, we want to use the “runlab.do” file to compile and run the simulation. To do that,in the transcript pane type “do runlab.do” and hit enter. Note that hitting tab when youhave typed “do r” already will auto-complete with the full command.

Once you execute the command, ModelSim will simulate the execution of the design, anddisplay the results in the simulation window. Time moves from left (start of simulation) toright (end of simulation), with a green line for each input and output of the design. When thegreen line is up, it means that signal is true, while if the green line is down it means the signalis false. Note that if you see any red or blue lines it means there is a problem in your Verilogfiles – check that you have done all of the previous steps correctly.

6. Navigating the simulationAt this point you should have successfully run the simulation, but the waveform window israther small and hard to see. Let’s explore the navigation commands in ModelSim.Click on the waveform window, and look at the toolbars near the top of the ModelSimwindow. We first want to use the zoom commands:Use the left two commands ( and – magnifying glass) to zoom so that the green waves fillthe waveform window. Notice that the scrollbar at the bottom of the waveform window nowbecomes useful, allowing us to move around in the simulation. The time for each horizontalposition is also shown at the bottom of the window.We can also move around in the simulation and see the value of the signals. Look for thecursor, a yellow vertical line in the waveform viewer, with the time in yellow at the bottom.

Left-click on one of the green lines in the waveform viewer. The cursor moves to thatlocation, and next to each signal name appears a 0 or 1 value. This means that, at the timespecified by the cursor, the signals are at those given values. If the “out” signal says “St1” or“St0” that’s fine – just another way to say 1 or 0.Left-click in the waveform window at another point on the green waveforms. The cursor willjump to that position, and the Msgs field will update with the values of all signals. This willallow you to move to whatever position is of concern, and look at each signal value.We can also move to points of interest for a given signal. Click on the green waveform forthe “i1” signal. The “i1” label in the leftmost waveform column should become highlightedin white. Play with the six cursor movement commands to see what they will do:

These commands will help you quickly move through the simulation, finding situations ofinterest.Now that we have zoomed in to better display our design, and put a cursor at a point ofinterest, we will often want to save these setting into a file, so that our next simulation runwill return back to this position. To do that, click somewhere in the grey columns of thewaveform pane, then select “File Save Format” from the toolbar. You should overwrite thefile “mux2 1 wave.do”. In this way, when you rerun simulation, it will have the waveformwindow set up exactly the way we just left it, though with new simulation results if youchanged the Verilog files (i.e. fixed any bugs there are in your design ). Verify this by clickingon the Transcript window and typing “do runlab.do” now.7. More complex designsThe 2:1 mux design was set up to be a simple, single-file design to get you started quickly.But, real designs will have multiple files, and won’t have all the scripts set up for you. Let’smake a more complex design, and show you how to build new designs, especially how towork with the various ModelSim support files.Make sure you have exited out of both ModelSim and Quartus.We’ll now build a 4:1 mux out of the 2:1 muxes. We could go through all the steps above,but why bother? Instead, simply make a copy of the lab1 directory, and call it lab1a. So youshould now have an ee271labs directory with both a lab1 and lab1a subfolder. In this waywe can use the lab1 directory as a template, without overwriting all of our old work. Go intodirectory lab1a and double-click “DE1 SoC.qpf”, the Quartus II project file. This startsQuartus in the new directory, with the mux2 1 design already there. We’re going to need anew file for our mux4 1, so do File New and create a SystemVerilog HDL file. Do File SaveAs and name it mux4 1.sv. In the file, type or cut-n-paste the following design for themux4 1:

module mux4 1(out, i00, i01, i10, i11, sel0, sel1);output out;input i00, i01, i10, i11, sel0, sel1;wire v0, v1;mux2 1 m0(.out(v0), .i0(i00), .i1(i01), .sel(sel0));mux2 1 m1(.out(v1), .i0(i10), .i1(i11), .sel(sel0));mux2 1 m (.out(out), .i0(v0), .i1(v1), .sel(sel1));endmodulemodule mux4 1 testbench();reg i00, i01, i10, i11, sel0, sel1;wire out;mux4 1 dut (.out, .i00, .i01, .i10, .i11, .sel0, .sel1);integer i;initial beginfor(i 0; i 64; i ) begin{sel1, sel0, i00, i01, i10, i11} i; #10;endendendmoduleNotice that this design uses the mux2 1 as a subroutine. Notice also that this file has its owntestbench – every Verilog module should have a testbench, because the quickest way to geta working design is to test each submodule as you write it.To check that the design is correct, right-click on “mux4 1.sv” and “Set as Top-level Entity”,then run Analysis & Synthesis from the toolbar. If Quartus doesn’t say “Analysis & Synthesiswas successful”, fix whatever errors there are.Before we perform simulation, we need to fix the runlab.do file to work for the new design.Outside of Quartus right-click on runlab.do in a Windows File Explorer, and open the file (useWordPad, NotePad, or whatever text editor is on your machine). We need to make thefollowing modifications to the file:1. Add a line to compile the mux4 1.sv file. Duplicate the current line that starts with “vlog”,and change “mux2 1” to “mux4 1” in the duplicate. For all Quartus designs, you will haveone “vlog” line for each Verilog file in your design.2. Change the module being simulated. Edit the line starting “vsim” to end withmux4 1 testbench, instead of mux2 1 testbench. This tells ModelSim what unit you aretesting right now.

3. Change the file that contains the waveform setting file. Edit the line starting