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Using the ModelSim-Intel FPGASimulator with Verilog TestbenchesFor Quartus Prime 18.01IntroductionThis tutorial introduces the simulation of Verilog code using the ModelSim-Intel FPGA simulator. We assume thatyou are using ModelSim-Intel FPGA Starter Edition version 18.0. This software can be downloaded and installedfrom the Download Center for Intel FPGAs. In this download center, you can select release 18.0 of the QuartusPrime Lite Edition, and then on the Individual Files tab choose to download and install the ModelSim-IntelFPGA Starter Edition software. We assume that you are using a computer that is running the Windows operatingsystem. If you are using the Linux operating system then minor differences to the instructions would apply, such asusing a / filesystem delimiter rather than the \ delimiter that is used with Windows.Contents: Getting Started with ModelSim Simulating a Sequential Circuit Simulating a Circuit that Includes a Memory Module Setting up a ModelSim Simulation Using the ModelSim Graphical User InterfaceRequirements: ModelSim-Intel FPGA Starter Edition software A computer running either Microsoft* Windows* (version 10 is recommended) or Linux (Ubuntu, or a similarLinux distribution). The computer would typically be either a desktop computer or laptop, and is used to runthe ModelSim software.Optional: Intel Quartus Prime software A DE-series development and education board, such as the DE1-SoC board. These boards are described onIntel’s FPGA University Program website, and are available from the manufacturer Terasic Technologies.Intel Corporation - FPGA University ProgramJune 20181

U SING THE M ODEL S IM -I NTEL FPGA S IMULATOR WITH V ERILOG T ESTBENCHES2For Quartus Prime 18.0Getting StartedThe ModelSim Simulator is a sophisticated and powerful tool that supports a variety of usage models. In this tutorialwe focus on only one design flow: using the ModelSim software as a stand-alone program to perform functionalsimulations, with simulation inputs specified in a testbench, and with simulator commands provided via script files.Other possible design flows for using ModelSim include invoking it from within the Intel Quartus Prime software,performing timing simulations, and specifying simulation inputs by drawing waveforms in a graphical editor insteadof using a testbench. These flows are not described here, but can be found in other documentation that is availableon the Internet.To introduce the ModelSim software, we will first open an existing simulation example. The example is a multibitadder named Addern, and is included as part of the design files provided along with this tutorial. Copy the Addernfiles to a folder on your computer, such as C:\ModelSim Tutorial\Addern. In the Addern folder there is a Verilogsource-code file called Addern.v and a subfolder named ModelSim. The Addern.v file, shown in Figure 1, is theVerilog code that will be simulated in this part of the tutorial. We will specify signal values for the adder’s inputs,Cin, X, and Y, and then the ModelSim simulator will generate corresponding values for the outputs, Sum and Cout.// A multi-bit addermodule Addern (Cin, X, Y, Sum, Cout);parameter n 16;input Cin;input [n-1:0] X, Y;output [n-1:0] Sum;output Cout;assign {Cout, Sum} X Y Cin;endmoduleFigure 1. Verilog code for the multibit adder.We will use three files included in the ModelSim subfolder to control the ModelSim simulator. The files are namedtestbench.v, testbench.tcl, and wave.do.The testbench.v file is a style of Verilog code known as a testbench. The purpose of a testbench is to instantiate aVerilog module that is to be simulated, and to specify values for its inputs at various simulation times. In this case themodule to be simulated is our multibit adder, which we refer to as the design under test (DUT). The first statementin the Verilog testbench, illustrated in Figure 2, is called a timescale compiler directive. Its first argument sets theunits of simulation time to 1 nanosecond. The user can specify values for the inputs to the DUT in terms of thesetime units, as we will illustrate shortly. The second argument sets the resolution of the simulation to 1 picosecond.This parameter specifies the granularity of time for which ModelSim evaluates signal values during a simulation.We will use these parameters for all of our simulations in this tutorial.Line 2 is the start of the testbench module, which has no inputs or outputs. In Lines 4 and 5 we declare the signalsCin, X, and Y, which will be used as the inputs to the DUT. Values will be assigned at various simulation times tothese signals in the testbench code. Verilog syntax requires that these signals have the type reg as given in the figure.When a value is specified in the testbench code for a signal with the reg type, the signal maintains this value until2Intel Corporation - FPGA University ProgramJune 2018

U SING THE M ODEL S IM -I NTEL FPGA S IMULATOR WITH V ERILOG T ESTBENCHESFor Quartus Prime 18.0it is changed again in the testbench. Lines 7 and 8 in Figure 2 declare the signals Sum and Cout, which will beconnected to the outputs of the DUT. These signals, whose values are determined by the behavior of the DUT duringthe simulation, have to be declared with the type wire as given in the code.The Addern module, our design under test, is instantiated in Line 11 of the testbench. The Addern inputs and outputsare attached to the signals declared previously in Lines 4 to 8 of the testbench.Lines 14 to 22 provide an initial block. It is is used to assign values to the reg signals that provide inputs to the DUT.The initial block starts executing at the beginning of simulation time, so that line 16 initializes the signals X, Y, andCin to 0 at simulation time 0. Line 17 specifies that after 20 simulation time units the value of the input Y changesto 10. Since the unit of simulation time is set to 1 ns by the timescale directive in Line 1, this means that Y changesto the value 10 at 20 ns in simulation time. Line 18 specifies that after another 20 ns, meaning at 40 ns in simulationtime, input X changes to 10. The rest of the initial block specifies various values for the adder inputs at 20 ns 23‘timescale 1ns / 1psmodule testbench ( );// reg signals provide inputs to the design under testreg Cin;reg [15:0] X, Y;// wire signals are used for outputswire [15:0] Sum;wire Cout;// instantiate the design under testAddern U1 (Cin, X, Y, Sum, Cout);// assign signal values at various simulation timesinitialbeginX 0; Y 0; Cin 0;#20 X 0; Y 10; Cin 0;#20 X 10; Y 10; Cin 0;#20 X 10; Y 10; Cin 1;#20 X 16’hFFF0; Y 16’hF; Cin 0;#20 X 16’hFFF0; Y 16’hF; Cin 1;end // initialendmoduleFigure 2. The Verilog testbench code.Open the ModelSim software to reach the window shown in Figure 3. Click on the Transcript window at the bottomof the figure and then use the cd command to navigate to the ModelSim folder for the multibit adder. For example,in our case we would type cd C:/ModelSim Tutorial/Addern/ModelSim. Note that ModelSim uses the/ symbol to navigate between filesystem folders, even though the Windows operating system uses the \ symbol forthis purpose. Next, we wish to run a series of simulator commands that are included in the script file testbench.tcl.Intel Corporation - FPGA University ProgramJune 20183

U SING THE M ODEL S IM -I NTEL FPGA S IMULATOR WITH V ERILOG T ESTBENCHESFor Quartus Prime 18.0Figure 3. The ModelSim window.Figure 4 shows the contents of the script testbench.tcl. First, the quit command is invoked to ensure that nosimulation is already running. Then, in Line 4 the vlib command is executed to create a work design library;ModelSim stores compilation/simulation results in this working library. The Verilog compiler is invoked in Line 7to compile the source code for the Addern module, which is in the parent folder (./), and in Line 9 to compiletestbench.v in the current folder. The simulation is started by the vsim command in Line 11. It includes somesimulation libraries for Intel FPGAs that may be needed by ModelSim. If the included libraries aren’t required forthe current design, then they will be ignored during the simulation. Line 13 in Figure 4 executes the commanddo wave.do. The do command is used to execute other ModelSim commands provided in a file. In this case thefile wave.do, which will be described shortly, contains various commands that are used to configure the ModelSimwaveform-display window. The final command in Figure 6 advances the simulation by a desired amount of time,which in this case is 120 ns.To run the script, in the Transcript window type the command do testbench.tcl. ModelSim will execute thecommands in this script and then update its graphical user interface to show the simulation results. The updatedModelSim window after running the testbench.tcl script is illustrated in Figure 5.4Intel Corporation - FPGA University ProgramJune 2018

U SING THE M ODEL S IM -I NTEL FPGA S IMULATOR WITH V ERILOG T ESTBENCHES123456789101112131415For Quartus Prime 18.0# stop any simulation that is currently runningquit -sim# create the default "work" libraryvlib work;# compile the Verilog source code in the parent foldervlog ./*.v# compile the Verilog code of the testbenchvlog *.v# start the Simulator, including some librariesvsim work.testbench -Lf 220model -Lf altera mf ver -Lfverilog# show waveforms specified in wave.dodo wave.do# advance the simulation the desired amount of timerun 120 nsFigure 4. The testbench.tcl file.Figure 5. The updated ModelSim window.Intel Corporation - FPGA University ProgramJune 20185

U SING THE M ODEL S IM -I NTEL FPGA S IMULATOR WITH V ERILOG T ESTBENCHESFor Quartus Prime 18.0The wave.do file used for this design example appears in Figure 6. It specifies in Lines 3 to 12 which signalwaveforms should be displayed in the simulation results, and also includes a number of settings related to the display.To add or delete waveforms in the display you can manually edit the wave.do file using any text editor, or you canselect which waveforms should be displayed by using the ModelSim graphical user interface. Referring to Figure 5,changes to the displayed waveforms can be selected by right-clicking in the waveform window. Waveforms canbe added to the display by selecting a signal in the Objects window and then dragging-and-dropping that signalname into the Wave window. A more detailed discussion about commands available in the graphical user interfaceis provided in Appendix A.Quit the ModelSim software to complete this part of the tutorial. To quit the program you can either select theFile Quit command, or type exit in the Transcript window, or just click on the X in the upper-right corner ofthe ModelSim 27282930onerror {resume}quietly WaveActivateNextPane {} 0add wave -noupdate -label Cin /testbench/Cinadd wave -noupdate -label X -radix hexadecimal /testbench/Xadd wave -noupdate -label Y -radix hexadecimal /testbench/Yadd wave -noupdate -label Cout /testbench/Coutadd wave -noupdate -divider Adderadd wave -noupdate -label Cin /testbench/U1/Cinadd wave -noupdate -label X -radix hexadecimal /testbench/U1/Xadd wave -noupdate -label Y -radix hexadecimal /testbench/U1/Yadd wave -noupdate -label Sum -radix hexadecimal /testbench/U1/Sumadd wave -noupdate -label Cout /testbench/U1/CoutTreeUpdate [SetDefaultTree]WaveRestoreCursors {{Cursor 1} {20000 ps} 0}quietly wave cursor active 1configure wave -namecolwidth 73configure wave -valuecolwidth 64configure wave -justifyvalue leftconfigure wave -signalnamewidth 0configure wave -snapdistance 10configure wave -datasetprefix 0configure wave -rowmargin 4configure wave -childrowmargin 2configure wave -gridoffset 0configure wave -gridperiod 1configure wave -griddelta 40configure wave -timeline 0configure wave -timelineunits nsupdateWaveRestoreZoom {0 ps} {120 ns}Figure 6. The wave.do file.6Intel Corporation - FPGA University ProgramJune 2018

U SING THE M ODEL S IM -I NTEL FPGA S IMULATOR WITH V ERILOG T ESTBENCHES3For Quartus Prime 18.0Simulating a Sequential CircuitAnother ModelSim example, called Accumulate, is included as part of the design files for this tutorial. Copy theAccumulate example to a folder on your computer, such as C:\ModelSim Tutorial\Accumulate. In the Accumulatefolder there is a Verilog source-code file called Accumulate.v and a subfolder named ModelSim. The Accumulate.vfile, which provides the Verilog code that we will simulate, is shown in Figure 7. It represents the logic circuitillustrated in Figure 8, which includes an adder, register, and down-counter. The purpose of this circuit is to addtogether, or accumulate, values of the input X for each clock cycle until the counter reaches zero.The Accumulate module in Figure 7 has ports KEY, CLOCK 50, SW, and LEDR because the module is intended tobe implemented on a DE-series board that features an Intel FPGA, such as the DE1-SoC board. After simulating theVerilog code to verify its correct operation, you may wish to compile it using the Quartus Prime CAD tools and thendownload and test the resulting circuit on a board.module Accumulate (KEY, CLOCK 50, SW, LEDR);input [0:0] KEY;input CLOCK 50;input [9:0] SW;output [9:0] LEDR;wire Clock, Resetn, z;wire [4:0] X, Y;reg [9:0] Sum;reg [4:0] Count;assignassignassignassignClock CLOCK 50;Resetn KEY[0];X SW[4:0];Y SW[9:5];always @(posedge Clock)if (Resetn 1’b0)Sum 0;else if (z 1’b1)Sum Sum X;// synchronous clear of the accumulatoralways @(posedge Clock)if (Resetn 1’b0)// synchronous load of the counterCount Y;else if (z 1’b1)Count Count - 1’b1;assign z Count;assign LEDR Sum;endmoduleFigure 7. Verilog code for the accumulator.Intel Corporation - FPGA University ProgramJune 20187

U SING THE M ODEL S IM -I NTEL FPGA S IMULAT