Transcription

QUARTUS AND MODELSIMQUICK STARTDavid Tietz(Modified by H. Lam 2012Update by Shaon Yousuf 2013)Department of Electrical and Computer Engineering

Contents1. Installation2. Create a Quartus II Project3. Adding Design Files4. Setting Up the EDA Simulator Execution Path5. Compiling the Design6. Creating a Project in ModelSim-Altera7. Understanding a Testbench File8. Compiling a Project in ModelSim-Altera9. Running a Functional Simulation10. Running a Timing Simulation11. Results2

Installation1. Download and install the newest version of Quartus II Web Edition Software andModelSim-Altera Starter Edition uartus-ii/web-edition/qts-we-index.html Be sure the checkbox for Quartus II Programmer and SignalTap II is checked.Create a Quartus II ProjectOnce you start Quartus II web edition. You must first create a new project by selection NewProject Wizard from the welcome screen:1. At the Introduction page, click next.2. Start by creating a new directory and project name, shown in Figure 1. Save itsomewhere you can access it easily (e.g., /Documents/EEL4712/SimpleLogic). Thenclick next.Figure 13. In the next page, you would normally add design files to your project, if this is yourfirst lab, you don’t have any to import, so just click next.4. In the family and device setting step, select ‘Auto device selected by the Fitter’ orselect the correct device we will be using for EEL 4712, shown in Figure 2 then clicknext.3

Figure 25. In EDA Tool Settings, select the following (i.e., ModelSim-Altera) from the pull downmenus, shown in Table 1, and click next:Tool TypeDesign Entry/SynthesisSimulationTiming AnalysisFormat VerificationTool Name None ModelSim-Altera None None Table 16. On the summary page, click finish.Adding Design Files1. (a) From the file menu, select new. From the Menu, select the type of design file youwould like to create (in this case VHDL), then click OK, as shown in Figure 3.Type in the VHDL code from SimpleLogic.vhd4

Figure 31. (b) Alternatively, you can add the file (SimpleLogic.vhd) to the project (without havingto type it in:Click Project Add/Remove File from Project Browse to the directory and select SimpleLogic.vhdClick Add and then OK2. If necessary, confirm that the design file was added to the current project, by click fromthe top menu: Project Add Current File to Project.Setting Up the EDA Simulator Execution PathTo run an EDA simulator (e.g. Modelsim-Altera) automatically from the Quartus II software usingthe NativeLink feature, specify the path to your simulation tool by performing the following steps:1. On the Tools menu, click Options. The Options dialog box appears.2. In the Category list, under the General category, select EDA Tool Options.3. The Options window should look like Figure 4. In the Modelsim-Altera entry, the locationof executable should be something like “C:\altera\13.0sp1\modelsim ase\win32aloem”.4. If not, then browse to the directory containing the executable of the Modelsim-Alterasimulator. (Again, path should be like “C:\altera\13.0sp1\modelsim ase\win32aloem”.)5. Click OK.5

Compiling the DesignOnce you have all the design files you need in place, you are ready to compile:1. On the top menu, select: Processing Start Compilation.2. The message window below will show compilation status, and you will also be shown acompilation report window. If the design compiles successfully, you can close out thereport.Figure 46

Compilation in ModelSim-AlteraNow that you have created and compiled the project in Quartus II. You are ready to useModelSim to perform the testbench simulations, but first you need to compile your design filesin ModelSim1. Invoke ModelSim from Quartus: Tools Run Simulation Tool RTL Simulation2. On ModelSim open the compile window by clicking Compile Compile3. Compile the following files:a. SimpleLogic.vho (should be in the simulation/modelsim directory)b. SimpleLogic tb.vhd (Provided to you in Lab1vhdlFiles.zip and placed by you insome directory)4. Click Done and open the library view if it’s not already open (by selecting View Library) and verify the red circled portions as shown in Figure 5 are there.5. If there are errors, try compiling again because an incorrect compilation order can causethis problem. If there are errors in the testbench, you likely didn’t name your I/Ocorrectly in your Quartus design file (SimpleLogic.vhd).Appears after you compileSimpleLogic tb.vhdAppears after you compileSimpleLogic.vhoFigure 57

Understanding a Testbench FileTestbench files are used to test your design files as against a set of input test signals. Input testsignals are generated and applied to the unit under test (UUT) within the test bench. Figure 6 is atestbench file we used for this tutorial.Declaring all input andoutput test signalsWait betweenchanging inputvaluesMapping input test signalsto component signals ofUUT (i.e., SimpleLogic)Setting values toinput test signalsFigure 6For future designs, you will need to make or modify the above testbench file to fit the needs ofthe design you are trying to simulate. You will need to declare the test signals you will use, portmap them to correct component signals from the Quartus design, and then setup the actual signaltransitions.8

Running a Functional SimulationIn a functional simulation, you will simulate your design based on a functional stand point. Inother words, delays through the system will not be taken into account. To run a functionalsimulation:1. Click Simulate Start Simulation.2. On the Design tab select work SimpleLogic tb, which is the testbench. Click OK.3. Two simulation windows should load: Object window and Wave window. If not, youcan always load them yourself by clicking the View menu and checking the appropriatewindow.4. Generally you want to display all the test signals in the Wave window. To do so, click inthe Objects window Click Add - To Wave - Signals in RegionAlternatively, you can display only selected signals in the Wave window: In the Objects window, select the signals you would like to monitor and drag theminto the Wave window (or copy and paste).5. Click Simulate Run Run -All.6. You can use ‘Ctrl ’ and ‘Ctrl -‘ to zoom in and out. Figure 7 shows the results of thesimulation.Figure 87Figure9

Running a Timing SimulationIn a timing simulation, you will simulate your design based on a timing stand point. In otherwords, delays through the system will be included and will affect the performance of yourdesign. To run a timing simulation:1. Make sure the simulation currently running is complete by clicking Simulation EndSimulation.2. Quartus creates an .sdo file to annotate simulation with actual propagation delays. Toinclude this in your ModelSim project:a. Select the SDF tab (on the dialog box that comes up after Start Simulation).b. Add the SimpleLogic.sdo file that is in the quartus project/simulation/modelsimdirectory.c. This should be same directory as the .vho file that you previously added.d. In the “Apply to Region” text box, make sure to type /UUT (this is the same labelused in the testbench file for that region of component instantiation).3. On the Design tab select work- SimpleLogic tb, which is the testbench. Click OK. Threesimulation screens will load.4. In the Objects window, select the signals you would like to monitor and drag them intothe Wave view.5. Click Simulate Run Run -All.6. Figure 8 shows the results of the timing simulation.Figure 9Figure 810