Transcription

University of TwenteFaculty of Electrical Engineering,Mathematics and Computer ScienceVHDL tutorialFor internal use only E. MolenkampJanuary 2016

Contents12Introduction . 3Simulation with ModelSim . 42.1Analyse/Compile . 52.2Simulate. 72.2.1 Script file with the stimuli . 102.2.2 Stimuli generation with VHDL . 102.3Simulation model . 153Synthesis with Quartus II . 163.1Start Quartus II . 173.2Create a new project . 173.3Top level of the design . 213.4Compile ( synthesize). 213.5RTL viewer/Technology Map Viewer . 224Post simulation . 235Constraint file . 266Programming the device. 277Synthesis with Precision RTL . 28Appendix A An alternative description for count . 31Appendix BVerification of a design via simulation. 32Appendix CModelSim/QuestaSim if no project is used . 34Appendix D Compiling Altera libraries with QuestaSim . 35Appendix EProgramming Cyclone II (DE1) . 36Appendix FProgramming Cyclone V (DE1-SoC) . 37Appendix G Datasheet Report. 402

1 IntroductionVHDL is the hardware description language used in this course. It is one of the languagesused in many companies in Europe. Many tools are available for simulation and synthesis. Wehave chosen a toolset that can also be installed at home (no license required).VHDL simulationModelSim-Altera StarterIncludes post simulationlibraries for Altera devices.(Windows/Linux)HomeX(Optimization is disabled inthe free version.)QuestaSimInstalled on the lab machinesand supports PSL.VHDL SynthesisFor post simulation of a designthe vendor libraries should becompiled first.Quartus IIQuartus II web edition(free)(windows/linux)Precision RTLIs a technology independentsynthesis tool.UniversityX(windows)XXXX(windows)XTable 1: tools used in the load/altera design/quartus we/dnl-quartus we.jspNotes:1. The free web editions of the Quartus II software support only the latest devices of a familye.g. If you use a “Cyclone I” device use version 11.0 SP1. If you use a “Cyclone II” device use version 13.0 SP1. This device is used in thepopular DE1 development board. If you use a “Cyclone V” device use version 14.0, 15.0(post simulation with timing is not for Cyclone V devices. The *.sdo file is not createdonly a functional post simulation is possible (file *.vho).2. The interface of the different versions may slightly be different.3

2 Simulation with ModelSimIn this tutorial a circuit is used that counts the number of ones in the input 18.19.20.21.LIBRARY ieee;USE ieee.std logic 1164.ALL;ENTITY count ISGENERIC (w : positive : 8);PORT (a : IN std logic vector(w-1 DOWNTO 0);q : OUT integer RANGE 0 TO w);END count;ARCHITECTURE behaviour OF count ISFUNCTION cnt (a:std logic vector) RETURN integer ISVARIABLE nmb : INTEGER RANGE 0 TO a'LENGTH;BEGINnmb : 0;FOR i IN a'RANGE LOOPIF a(i) '1' THEN nmb: nmb 1; END IF;END LOOP;RETURN nmb;END cnt;BEGINq cnt(a);END behaviour;Figure 1: behavioural description of count (the line numbers are not part off the VHDL code!)Generic w, line 4, is a global constant with value 8. Input a of this design is w bits wide. Theoutput q is an integer value. The width of the input is w, therefore the number of ones must bebetween 0 and w (inclusive). A range constraint is added to the integer type. The rangeconstraint is not necessary but it is used for documentation and will guide the synthesisprocess.There are many ways to count the number of ones in an array. In the architecture (figure 1) afunction is declared that takes care of this. This function has as input an object of typestd logic vector. A std logic vector is an unconstrained array; the length of this type is not(yet) known! The reason to use an unconstrained array as input is to make the design genericwith respect to the width of the input. At the location of the function call, line 20, the range ofthe input is known.The algorithm used in the function is straightforward. With a loop statement all elements ofthe inputs are examined. The only problem is: what are the vector indices? The attribute'range is used for this. If the function is called with an object that is declared asstd logic vector(5 to 36) then within the function the a'range is replaced with 5 to 36.This design is simulated using ModelSim.4

2.1 Analyse/Compilefigure 2: ModelSim screenModelSim starts with the window shown in figure 2. In this tutorial a project is used. So wewill first create a project:File New ProjectChoose a “project name” and “Project location”. Do not change the default library name‘work’ and also select the option “copy library mappings”.5

Select “add existing file” and browse to the directory with the source file and select the file“count.vhd”.Click on OKand close the “add items to the Project”Right-click on the file “count.vhd” compile compile selectedThe design is compiled into library work. You can verify this by clicking the tab libraryFigure 3: the result after compilationThe top window shows the libraries and the bottom window (“Transcript”) is used forcommands entered by the user and for reporting information to the user. You can dock (as6

shown above) and undock (a separate window) using the arrow in the upper right corner of awindow.By default an analysed VHDL design is stored in a library work.Notes1 The content of the library work is managed by ModelSim. Do not change thecontents of this library outside ModelSim nor place your source files in thatlibrary!2 If you want to delete a compiled design from the library right click the design (tablibrary should be selected) in the GUI and select delete. Your source file is still in theproject.3 If you want to remove a file from the project right click the file (tab project should beselected) in the GUI and select remove from project.Important: if the file was compiled then the design units that were in the file are notremoved from the library!4 ModelSim uses the term Compile instead of Analysis.5 For the VHDL object signal ModelSim uses also the term object.6 For the VHDL object variable ModelSim uses also the term local. During debuggingof a design locals are not visible by default. This can be changed:tab View select “locals”.2.2 SimulateClick with the right mouse button on the architecture name ‘behaviour’ and you can load yourdesign in the simulator (or you can use menu simulate start simulation).Figure 3a: Selection of the design that should be simulated7

Note:In the ModelSim-Altera starter edition “Enable optimization” is disabled. In case alicenced version of ModelSim/QuestaSim is used optimizations it is on by default.Optimization improves simulation speed but during debugging not all signals andvariables are visible. Therefore select ‘full visibility’ in the tab OptimizationOptions.Select the design and click OKDuring simulation you probably like to see some waveforms therefore enter:add wave * return (In stead of * you may enter a list with the signal names separated with a comma).Notes1. If the signals a and q are not shown in the window wave you probably did not selectcount in the window instance. Select count and repeat the command “add wave *”2. The windows objects and locals show respectively the signals and variables that arevisible at the selected instance. Select line 20 and you will also see the generic w.3. You can also drag and drop objects and locals to the wave window.Figure 3b: Selection of the design that should be simulated8

With the run command you perform a simulation:run 200 ns enter Why are the input values ‘U’?With the force command you can apply an input pattern to a:force a 'b01100011 enter 1run 100 ns enter Try it with some other values for a.You can assign multiple values to the input with:force a 'b11111111, 'b00111111 10 ns, 'b11110101 20 ns enter run 100 ns enter Try it.Note:In VHDL descriptions a space is required between the number and the time unit. So“100ns” is not correct, it must be but “100 ns”. ModelSim will report a warning:Warning: [4] path . file ( line number ): (vcom-1207) An abstract literal andan identifier must have a separator between them.It is probably only a warning because the examples in the first VHDL standard (1987)did not have the spaces .The user interface of ModelSim supports both.1The default radix depends on de version of ModelSim/QuestaSim. In the past it was binary. E.g.force a 01100011 is the binary pattern 01100011. As of QuestaSim version “Sim-64-10.2” this the default ischanged to hexadecimal. So 01100011 is hexadecimal and equal to binary 100010000000000000001001 and thelowest 8 bits are assigned to input a. Explicitly add a radix avoids confusion, e.g.force a 'b1110 for binaryforce a 'hDfor hexadecimalforce a 'd14for decimal9

Notes:1. If the wave window is selected you can zoom in and out with the buttons:- zoom in- zoom out- zoom full- zoom in on active cursor. (Select a point in the wave window and a cursor appears.)2. Multiple cursors are possible in the wave window. Right-click the bottom black line inthe wave window. The time differences between the cursors are also shown.2.2.1 Script file with the stimuliA tool dependent solution to apply stimuli is using a script file. A simple example is givenbeneath. Create a file “demo.do” with the following contents:force a 'b00011111run 100 nsforce a 'b10100000run 100 nsIn ModelSim this script file is executed with the command:do demo.do return Notes1A synchronous design has a clock. Assume signal clk is the clock. A repetitive patternis created with the command:force clk 0, 1 50 ns -repeat 100 ns(DO NOT copy from the pdf file because characters look the same, but may bedifferent)(this can also be used for other signals, not necessarily a clock.)2The ModelSim command “run -all” starts a simulation and will stop when no eventsare scheduled for the future. Do not use this command when a clock signal isgenerated with the method described in Note 1. Why not?3Commands that are entered in the transcript window can be written to a file with thecommand “write transcript filename ”. This file can be used as a script fileafterwards.2.2.2 Stimuli generation with VHDLApplying stimuli as presented in the previous section is tool dependent. It is also possible, andstrongly advised to be tool independent, to generate stimuli using VHDL.Finding test data for a design is not an easy task. In this example an exhaustive test is usedwhen the width of the data vector is not too large.LIBRARY ieee;USE ieee.std logic 1164.ALL;USE ieee.numeric std.ALL;ENTITY testset ISGENERIC (w : positive : 8);10

PORT (data : OUT std logic vector(w-1 DOWNTO 0));END testset;ARCHITECTURE set1 OF testset ISBEGINPROCESSBEGINdata (others '0');-- all zeroWAIT FOR 10 ns;data (others '1');WAIT FOR 10 ns;-- all oneFOR i IN 0 to 2**w-1 LOOPdata std logic vector(to unsigned(i,w));EXIT WHEN i 20; -- an exhaustive test is not performed if w is largeWAIT FOR 10 ns;END LOOP;WAIT; -- foreverEND PROCESS;END set1;Figure 4: simple test set.Figure 4 shows a simple test set. It contains one process statement. It first generates all zeros,waits for 10 ns, then it generates all ones and it waits again. Of course an exhaustive test ispossible. In the for-statement the loop parameter i (which is implicitly declared!) goes from 0to 2w-1. This integer value is converted to a bit pattern (using binary coding; also calledunsigned). For the conversion the function to unsigned is used. This function converts theinteger value i to an unsigned vector with length w. This function is located in a packagenumeric std (this package is in library ieee). However in case the generic ( constant) w islarge this is a time consuming task. Therefore in this example the loop is ended in case i isequal to 20. The process ends with wait. This means the process will not resume execution.Background information: numeric